1. Field of the Invention
The present invention relates to the field of integrated circuits. More specifically, the present invention relates to the manufacturing of CMOS and JFET transistors in a semiconductor substrate.
2. Discussion of the Related Art
Integrated circuits meant to perform logic functions are generally made in CMOS technology. To perform analog functions, bipolar components are generally preferred to be used. However, the simultaneous forming of CMOS and bipolar components on the same chip requires the use of so-called BICMOS lines which are more expensive than CMOS lines. Thus, in many cases, MOS transistors, for example, are used as input/output transistors to perform the analog functions. However, in low frequency applications, these transistors have the disadvantage of exhibiting a high output noise level due to carrier recombinations at the interface between silicon and silicon oxide. To compensate this problem, which is intrinsic since it is linked to the very surface operating principle of MOS transistors, MOS transistors of large dimensions which have the disadvantage of consuming a large amount of silicon are used.
Junction field-effect transistors (JFET) are known to have, with respect to insulated gate field effect transistors (MOSFET, or merely MOS), the advantage of a lower noise. However, up to now, the integration of these latter components requires introducing additional steps in a current CMOS technology manufacturing process. This would result in preferring BlCMOS technologies, with their cost disadvantages.